Dustin Peterson
Dustin Peterson
Universität Tübingen
Fachbereich Informatik
Lehrstuhl Eingebettete Systeme
Sand 13
72076 Tübingen
- Telefon
- +49 - (0) 70 71 - 29 - 75458
- Telefax
- +49 - (0) 70 71 - 29 - 50 62
- Büro
- Sand 13, B205
- Sprechstunde
- by appointment
Veröffentlichungen
2019
Fully-automated Synthesis of Power Management Controllers from UPF
by Dustin Peterson and Oliver BringmannIn Proceedings of the 24th Asia and South Pacific Design Automation Conference, pages 76–81. ACM, 2019.
Keywords: power design, power management, unified power format
Power-Gating Models for Rapid Design Exploration
by Dustin Peterson and Oliver BringmannIn 17th IEEE International New Circuits and Systems Conference (In Press), 2019.
2018
Detecting non-functional circuit activity in SoC designs
by Dustin Peterson, Yannick Boekle, and Oliver BringmannIn 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (): 464-469, 2018.
Keywords: clocks, embedded systems, integrated circuit design, system-on-chip, SoC designs, RTL design, internal graph representation, open source processor, commercial RTL simulator, average register toggle activity, exact same circuit output, clock gating architecture, commercial ASIP, nonfunctional circuit activity detection, Registers, Integrated circuit modeling, Clocks, Databases, Tools, Transfer functions, Boolean functions
2016
SMoSi: A framework for the derivation of sleep mode traces from RTL simulations
by Dustin Peterson and Oliver BringmannIn 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (): 330-335, 2016.
Keywords: integrated circuit design, integrated circuit modelling, low-power electronics, SMoSi, sleep mode trace generation, RTL simulations, idle time identification, power optimization, Ports (Computers), Redundancy, Transfer functions, Boolean functions, Data structures, Registers, Databases
Verfahren und System zur Verschlüsselung von Tastendrücken DE 10 2015 210 573 A1
by Sebastian Burg, Oliver Bringmann, and Dustin PetersonIn Deutsches Patent- und Markenamt, 2016.
Neues Konzept zur Steigerung der Zuverlaessigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs
by Konstantin Luebeck, David Morgenstern, Thomas Schweizer, Dustin Peterson, Wolfgang Rosenstiel, and Oliver BringmannIn Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016, 2016.
2015
End-to-Display Encryption: A Pixel-Domain Encryption with Security Benefit
by Sebastian Burg, Dustin Peterson, and Oliver BringmannIn Proceedings of the 3rd ACM Workshop on Information Hiding and Multimedia Security, pages 123–128. ACM, 2015.
Keywords: encryption, multimedia, physical security, security
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI
by Johannes M. Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, and Wolfgang RosenstielIn 2015 Design, Automation Test in Europe Conference Exhibition (DATE) (): 876-879, 2015.
Keywords: circuit analysis computing, reconfigurable architectures, silicon-on-insulator, temporal granularity, UTBB-FDSOI, SOI technology, performance characteristics, electrical task, substrate potential, dynamic voltage scaling, finer island sizes, body bias islands, body bias combinations, energy efficiency, timing constraints, combination based analysis tool, optimized body bias island partitions, body biasing levels, optimized body bias assignments, dynamic body biasing, dynamically switching body biases, power consumption, additional circuitry, switching overheads, application specific switching strategies, frequency scaling scenario, forward body biasing, dynamic reconfigurable processor, DRP design, Switches, Layout, Clocks, Optimization, Delays, Power demand
2013
A Fast and Accurate FPGA-Based Fault Injection System
by Thomas Schweizer, Dustin Peterson, Johannes M. Kühn, Thommy Kuhn, and Wolfgang RosenstielIn 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (): 236-236, 2013.
Keywords: fault simulation, field programmable gate arrays, hardware description languages, integrated circuit reliability, logic design, network routing, fast FPGA-based fault injection system, accurate FPGA-based fault injection system, RTL, port structure, placed and routed FPGA design, RT/gate-level circuit description, ISCAS’89 benchmark circuits, VHDL netlist, LEON3 system, fault injection tool, recompilation process, Circuit faults, Field programmable gate arrays, Emulation, Logic gates, Hardware, Libraries, Ports (Computers), FPGA synthesis, fault injection, fault emulation, reliability
Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection
by Johannes M. Kühn, Thomas Schweizer, Dustin Peterson, Thommy Kuhn, and Wolfgang RosenstielIn 2013 International Conference on Field-Programmable Technology (FPT) (): 462-465, 2013.
Keywords: fault tolerance, field programmable gate arrays, integrated circuit reliability, logic design, reconfigurable architectures, redundancy, system-on-chip, field programmable gate array, dynamic functional verification, dynamic remapping, TMR technique, triple modular redundancy technique, SoC design, system on chip design, coarse grained reconfigurable architectures, fault injection method, live FPGA, fault tolerant CGRA, testing reliability technique, Tunneling magnetoresistance, Reliability, System-on-chip, Circuit faults, Context, Computer architecture, Field programmable gate arrays
StML: Bridging the gap between FPGA design and HDL circuit description
by Dustin Peterson, Oliver Bringmann, Thomas Schweizer, and Wolfgang RosenstielIn 2013 International Conference on Field-Programmable Technology (FPT) (): 278-285, 2013.
Keywords: field programmable gate arrays, hardware description languages, integrated circuit design, FPGA design, HDL circuit description, StML, circuit partition, bidirectional mappings, static mapping library, EDA tool library, hardware debugging, RTL-based injection, area overhead, circuit granularity, fault injection method, Field programmable gate arrays, Integrated circuit modeling, Hardware design languages, Libraries, Layout, Wires, Routing
2012
Verfahren und Fahrzeugvorrichtung zur Datenfernabfrage DE 102012008283 A1
by Dustin PetersonIn Deutsches Patent- und Markenamt, 2012.
Forschungsprojekte
Lehre
| Advanced Topics in Embedded Systems | Summer 2016 Summer 2017 Summer 2018 Summer 2019 |
|---|---|
| Entwurf und Synthese Eingebetteter Systeme | Summer 2014 Summer 2015 Summer 2017 Summer 2018 |
| Modellierung und Analyse von Eingebetteten Systemen | Winter 2013 Winter 2014 Winter 2015 Winter 2016 Winter 2017 |
| Moderne Architekturen Eingebetteter Systeme | Winter 2019 |
| Programmierprojekt: Kunterbunter Hund | Summer 2013 |
| Programmierprojekt: Kunterbunter Hund 2.0 | Summer 2014 |
| Programmierprojekt: Kunterbunter Hund 3.0 | Summer 2015 |
| Programming Ultra Low Power Architectures | Summer 2014 Summer 2015 Summer 2016 Summer 2017 |
| Seminar: Embedded Systems | Summer 2013 |