Embedded Systems

Publications

2020

Automated Graph-Based Fault Injection Into Virtual Prototypes for Robustness Evaluation

by Jo Laufenberg, Thomas Kropf, and Oliver Bringmann
In 25 IEEE European Test Symposium ETS (): , 2020.

UltraTrail: A Configurable Ultra-Low Power TC-ResNet AI Accelerator for Efficient Keyword Spotting

by Paul Palomero Bernardo, Christoph Gerum, Adrian Frischknecht, Konstantin Lübeck, and Oliver Bringmann
In 2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pages 1-12, 2020.

2019

Towards Robust CNN-Based Object Detection through Augmentation with Synthetic Rain Variations

by Georg Volk, Stefan Müller, Alexander von Bernuth, Dennis Hospach, and Oliver Bringmann
In 2019 IEEE Intelligent Transportation Systems Conference (ITSC), pages 285-292, 2019.

Simulating Photo-Realistic Snow and Fog on Existing Images for Enhanced CNN Training and Evaluation

by Alexander von Bernuth, Georg Volk, and Oliver Bringmann
In 2019 IEEE Intelligent Transportation Systems Conference (ITSC), pages 41-46, 2019.

Benchmarking Robustness in Object Detection: Autonomous Driving when Winter is Coming

by Claudio Michaelis, Benjamin Mitzkus, Robert Geirhos, Evgenia Rusak, Oliver Bringmann, Alexander S. Ecker, Matthias Bethge, and Wieland Brendel
In CoRR abs/1907.07484, 2019.

Fully-automated Synthesis of Power Management Controllers from UPF

by Dustin Peterson and Oliver Bringmann
In Proceedings of the 24th Asia and South Pacific Design Automation Conference, pages 76–81. ACM, 2019.

Power-Gating Models for Rapid Design Exploration

by Dustin Peterson and Oliver Bringmann
In 17th IEEE International New Circuits and Systems Conference (In Press), 2019.

A Heterogeneous and Reconfigurable Embedded Architecture for Energy-Efficient Execution of Convolutional Neural Networks

by Konstantin Lübeck and Oliver Bringmann
In Architecture of Computing Systems (ARCS 2019), 2019.

Environment-aware Development of Robust Vision-based Cooperative Perception Systems

by Georg Volk, Alexander von Bernuth, and Oliver Bringmann
In 2019 IEEE Intelligent Vehicles Symposium (IV), 2019.

Systematic RISC-V based Firmware Design

by Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, and Wolfgang Kunz
In 2019 Forum for Specification and Design Languages, FDL 2019, Southampton, United Kingdom, September 2-4, 2019, 2019.

2018

A Software Reconfigurable Assertion Checking Unit for Run-Time Error Detection.

by Y. Zhou, S. Burg, O. Bringmann, and W. Rosenstiel
In European Test Symposium (ETS), 2018.

Advancing Source-Level Timing Simulation using Loop Acceleration

by Joscha Benz, Christoph Gerum, and Oliver Bringmann
In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1393–1398. IEEE, 2018.

Detecting non-functional circuit activity in SoC designs

by Dustin Peterson, Yannick Boekle, and Oliver Bringmann
In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (): 464-469, 2018.

Rendering Physically Correct Raindrops on Windshields for Robustness Verification of Camera-based Object Recognition

by Alexander von Bernuth, Georg Volk, and Oliver Bringmann
In 2018 IEEE Intelligent Vehicles Symposium (IV), pages 922–927, 2018.

2017

Ways of Improving the Precision of Eye Tracking Data: Controlling the Influence of Dirt and Dust on Pupil Detection

by W. Fuhl, T. C. Kübler, D. Hospach, O. Bringmann, W. Rosenstiel, and E. Kasneci
In Journal of Eye Movement Research 10(3), 2017.

Functional Safety of Sensor Systems in a Virtual Driving Environment

by Dennis Hospach, Stefan Mueller, and Oliver Bringmann
In AAET - Automatisiertes und vernetztes Fahren, pages 49–66, 2017.

Constraining Graph-based Test Case Generation by Fitness Landscaping

by Stefan Mueller, Jo Laufenberg, Joachim Gelrach, Thomas Kropf, and Oliver Bringmann
In 2017 Design, Automation Test in Europe Conference Exhibition DATE – REES Workshop, pages 52-54, 2017.

Timing Models for Fast Embedded Software Performance Analysis

by Oliver Bringmann, Christoph Gerum, and Sebastian Ottlik
In Handbook of Hardware/Software Codesign, pages 655–682, 2017.

Context-sensitive timing automata for fast source level simulation

by Sebastian Ottlik, Christoph Gerum, Alexander Viehl, Wolfgang Rosenstiel, and Oliver Bringmann
In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pages 512–517, 2017.

2016

Flexible In-Silicon Checking of Run-Time Programmable Assertions.

by Y. Zhou, O. Bringmann, and W. Rosenstiel
In On-Line Testing and Robust System Design (IOLTS), 2016.

Eine Tcl-Basierte Methode Zur Fehlerinjektion Und Fehlereffektsimulation/-Emulation Auf Xilinx-Fpgas

by T. Schweizer, M. Simsek, O. Bringmann, and W. Rosenstiel
In Proceedings Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV) Workshop 2016, 2016.

Linebased End-to-Display Encryption for Secure Documents

by S. Burg, P. Channakeshava, and O. Bringmann
In IEEE International Conference on Identity, Security and Behavior Analysis, 2016.

Simulation of Falling Rain for Robustness Testing of Video-Based Surround Sensing Systems

by Dennis Hospach, Stefan Mueller, Wolfgang Rosenstiel, and Oliver Bringmann
In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016.

SMoSi: A framework for the derivation of sleep mode traces from RTL simulations

by Dustin Peterson and Oliver Bringmann
In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (): 330-335, 2016.

Neues Konzept zur Steigerung der Zuverlaessigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs

by Konstantin Luebeck, David Morgenstern, Thomas Schweizer, Dustin Peterson, Wolfgang Rosenstiel, and Oliver Bringmann
In Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016, 2016.

Industriespionage verhindern mit End-to-Display-Verschlüsselung

by Sebastian Burg, Kevin Körner, and Stefan Müller
In ATZ elektronik 11, pages 70-74. Springer, 2016.

Combining Graph-based Guidance with Error Effect Simulation for Efficient Safety Analysis

by Jo Laufenberg, Sebastian Reiter, Alexander Viehl, Oliver Bringmann, Thomas Kropf, and Wolfgang Rosenstiel
In 2016 Design, Automation and Test in Europe Conference and Exhibition DATE (): 1132-1135, 2016.

2015

Framework for Varied Sensor Perception in Virtual Prototypes

by Stefan Mueller, Dennis Hospach, Joachim Gerlach, Oliver Bringmann, and Wolfgang Rosenstiel
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2015.

Robustness Evaluation and Improvement for Vision-based Advanced Driver Assistance Systems

by Stefan Mueller, Dennis Hospach, Joachim Gerlach, Oliver Bringmann, and Wolfgang Rosenstiel
In IEEE Intelligent Transportation Systems Conference (ITSC), 2015.

Spatial and temporal granularity limits of body biasing in UTBB-FDSOI

by Johannes M. Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, and Wolfgang Rosenstiel
In 2015 Design, Automation Test in Europe Conference Exhibition (DATE) (): 876-879, 2015.

End-to-Display Encryption: A Pixel-Domain Encryption with Security Benefit

by Sebastian Burg, Dustin Peterson, and Oliver Bringmann
In Proceedings of the 3rd ACM Workshop on Information Hiding and Multimedia Security, pages 123–128. ACM, 2015.

Graph Guided Error Effect Simulation

by Jo Laufenberg, Sebastian Reiter, Alexander Viehl, Oliver Bringmann, and Wolfgang Rosenstiel
In 2015 Embedded Systems Week ESWeek (): , 2015.

Improving accuracy of source level timing simulation for GPUs using a probabilistic resource model

by Christoph Gerum, Wolfgang Rosenstiel, and Oliver Bringmann
In 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2015, Samos, Greece, July 19-23, 2015, pages 18–25, 2015.

Source level performance simulation of GPU cores

by Christoph Gerum, Oliver Bringmann, and Wolfgang Rosenstiel
In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pages 217–222, 2015.

2014

Rotated Parallel Mapping: A Novel Approach for Mapping Data Parallel Applications on CGRAs

by S. Schulz, T. Schweizer, O. Bringmann, and W. Rosenstiel
In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014.

provoSATeur+glucose

by S. Burg, O. Bringmann, and T. Kropf
In Proceedings of SAT Competition 2014: Solver and Benchmark Descriptions B-2014-2. Department of Computer Science Series of Publications, 2014.

miniLoCeG+Glucose

by S. Burg, O. Bringmann, and T. Kropf
In Proceedings of SAT Competition 2014: Solver and Benchmark Descriptions B-2014-2. Department of Computer Science Series of Publications, 2014.

LoCEG: Local Preprocessing in SAT-Solving through Counter-Example Generation

by S. Burg, P. Heckeler, S. Huster, H. Eichelberger, J. Behrend, J. Ruf, T. Kropf, and O. Bringmann
In Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen 17, 2014.

Simulation and evaluation of the influence of sensor characteristics on vision based Advanced Driver Assistance Systems

by Dennis Hospach, Stefan Mueller, Joachim Gerlach, Oliver Bringmann, and Wolfgang Rosenstiel
In IEEE International Conference on Intelligent Transportation Systems, 2014.

2013

Ein Template-basierter Ansatz zur automatisierten Generierung von SystemC-Modellen aus IP-XACT-Beschreibungen

by Stefan Mueller, Yumin Zhou, Axel Braun, Joachim Gerlach, and Wolfgang Rosenstiel
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013.

A Fast and Accurate FPGA-Based Fault Injection System

by Thomas Schweizer, Dustin Peterson, Johannes M. Kühn, Thommy Kuhn, and Wolfgang Rosenstiel
In 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (): 236-236, 2013.

Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection

by Johannes M. Kühn, Thomas Schweizer, Dustin Peterson, Thommy Kuhn, and Wolfgang Rosenstiel
In 2013 International Conference on Field-Programmable Technology (FPT) (): 462-465, 2013.

StML: Bridging the gap between FPGA design and HDL circuit description

by Dustin Peterson, Oliver Bringmann, Thomas Schweizer, and Wolfgang Rosenstiel
In 2013 International Conference on Field-Programmable Technology (FPT) (): 278-285, 2013.

2010

Virtual Prototyping in Der Hardware- Und Software-Entwicklung Vernetzter Steuergeräte

by Andreas Braun, Stefan Lämmermann, Oliver Bringmann, and Wolfgang Rosenstiel
In AutoTest 2010, 2010.

Combining Software and Hardware LCS for Lightweight On-Chip Learning

by A. Bernauer, J. Zeppenfeld, O. Bringmann, A. Herkersdorf, and W. Rosenstiel
In DIPES/BICC 2010, IFIP AICT 329, pages 279–290. The original publication is available at http://springerlink.com/content/5h85381330886706/, 2010.

2009

Integration of High-Level Synthesis in ESL Platform Modeling by Automated Generation of Protocol Adapters

by J. Zimmermann, O. Bringmann, A. Braun, and W. Rosenstiel
In International Conference on Communication, Circuits and Systems (ICCCAS09), San Jose, USA), 2009.

Schnelle, Zyklengenaue Abschätzung Der Leistungsaufnahme Eingebetteter Prozessoren Auf Systemebene

by B. Sander, J. Schnerr, O. Bringmann, T. Schweizer, and W. Rosenstiel
In Workshop 2009 - Electronic Design Automation (EDA), 2009.

Generic Self-Adaptation to Reduce Design Effort for System-on-Chip

by A. Bernauer, O. Bringmann, and W. Rosenstiel
In IEEE International Conference on Self-Adaptive and Self-Organizing Systems, pages 126–135, 2009.

2008

Model-Based Platform Composition and Generation of Virtual Prototypes for Interconnected Microelectronic Systems

by Zimmermann, Bringmann, Gerlach, Schäfer, and Nageldinger
In edaWorkshop, 2008.

Holistic System Modeling and Refinement of Interconnected Microelectronic Systems

by Zimmermann, Bringmann, Gerlach, Schäfer, and Nageldinger
In MARTE Workshop, 2008.

Quantitative Bewertung Nicht-Funktionaler Systemanforderungen von System-on-Chip-Entwürfen

by Viehl, Sander, Bringmann, Yang, and Rosenstiel
In DASS, 2008.

Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties

by Viehl, Sander, Bringmann, and Rosenstiel
In Forum on Specification & Design Languages (FDL), 2008.

High-Performance Timing Simulation of Embedded Software

by Schnerr, Bringmann, Viehl, and Rosenstiel
In 45th Design Automation Conference (DAC), 2008.

Current State of ASoC Design Methodology

by Andreas Bernauer, Dirk Fritz, Björn Sander, Oliver Bringmann, and Wolfgang Rosenstiel
In Organic Computing - Controlled Self-Organization 08141. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, 2008.

2007

Entwurf Und Verifikation von Hardware/Software - Systemen

by J. Behrend, A. Braun, O. Bringmann, M. Krause, T. Kropf, S. Lämmermann, P. Nalla, W. Rosenstiel, J. Ruf, T. Schönwald, and A. Viehl u. J. Zimmermann
In Kooperationsmarkt Des Ekompass-Workshops, 2007.

2006

A SystemC-Based Software and Communication Refinement Framework for Distributed Embedded Systems

by M. Krause, O. Bringmann, and W. Rosenstiel
In 13. Workshop on Synthesis and System Integration of Mixed Information Technologies, 2006.

Communication Refinement and Target Software Generation Using SystemC

by M. Krause, O. Bringmann, and W. Rosenstiel
In GI/ITG/GMM Workshop Für Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen, 2006.

Towards a Framework and a Design Methodology for Autonomic SoC

by G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann, and W. Stechele.
In In 2nd IEEE International Conference on Autonomic Computing, 2006.

Virtual Prototyping Und Frühe Evaluierung von Systems-on-Chip Mit UML2 Und SysML

by A. Viehl, O. Bringmann, and W. Rosenstiel
In In Proceeding of GI/ITG/GMM Workshop Für Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen, 2006.

Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design

by A. Viehl, T. Schönwald, O. Bringmann, and W. Rosenstiel
In DATE, 2006.

Organic Computing at the System on Chip Level

by A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A. Bernauer, O. Bringmann, and W. Rosenstiel
In In Proceedings of the IFIP International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC). Springer, 2006.

Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoC

by A. Bouajila, A. Bernauer, A. Herkersdorf, W. Rosenstiel, O. Bringmann, and W. Stechele
In In Yi Pan, Franz j. Rammig, Hartmut Schmeck, and Mauricio Solar, Editors, 1st IFIP International Conference on Biologically Inspired Cooperative Computing (BICC) 216(107-113). Springer, 2006.

An Architecture for Runtime Evaluation of SoC Reliability

by A. Bernauer, O. Bringmann, W. Rosenstiel, A. Bouajila, W. Stechele, and A. Herkersdorf
In In INFORMATIK - Informatik Für Menschen, GI-Edition - Lecture Notes in Informatics 93: 177–185. Kölle Verlag, 2006.

2005

Cycle Accurate Binary Tanslation for Simulation Acceleration in Rapid Prototyping of SoCs

by J. Schnerr, O. Bringmann, and W. Rosenstiel
In In Proceedings of Design, Automation and Test in Europe (DATE), 2005.

Performance Analysis of Sequence Diagrams for SoC Design

by A. Viehl, O. Bringmann, and W. Rosenstiel
In In Proceedings of the 2nd UML for SoC-Design Workshop (UML-SoC), 42nd Design Automation Conference (DAC), pages 55–61, 2005.

Conflict Analysis in Multiprocess Synthesis for Optimized System Integration

by A. Siebenborn, O. Bringmann, and W. Rosenstiel
In International Conference on Hardware - Software Co-Design and System Synthesis, CODES+ISSS, 2005.

SystemC-Based Communication and Performance Analysis

by A. Braun, J. Gerlach, W. Rosenstiel, A. Siebenborn, and O. Bringmann
In Forum on Design and Specification Languages - FDL 2005, 2005.

2004

Communication Analysis for System on Chip Design

by A. Siebenborn, O. Bringmann, and W. Rosenstiel
In In Proceedings of Design, Automation and Test in Europe (DATE), 2004.

2002

Controller Estimation for FPGA Target Architectures during High-Level Synthesis

by C. Menn, O. Bringmann, and W. Rosenstiel
In 15th International Symposium on System Synthesis (ISSS), IEEE Computer Society Press, 2002.

Worst-Case Performance Analysis of Parallel, Communicating Software Processes

by A. Siebenborn, O. Bringmann, and W. Rosenstiel
In Proceedings of the Tenth International Symposium on Hardware/Software Co-Design (CODES), 2002.

2001

A VHDL Reuse Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis

by C. Hansen, O. Bringmann, and W. Rosenstiel
In System-on-Chip Methodologies & Design Languages, Edited by P.J. Ashenden, J.P. Mermet and r. Seepold (Buch);. Kluwer Academic Publishers, 2001.

2000

Target Architecture Oriented High-Level Synthesis for Multi-Fpga Based Emulation

by O. Bringmann, C. Menn, and W. Rosenstiel
In Proceedings of Design, Automation and Test in Europe (DATE), 2000.

Hierarchische Synthese Für Anwendungsspezifische Prototypenimplementierungen

by O. Bringmann and W. Rosenstiel
In It + It - Informationstechnik Und Technische Informatik 42. Oldenbourg Verlag, 2000.

1999

Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping

by O. Bringmann, W. Rosenstiel, K. Muth, Färber, F. Slomka, and H. Hofmann
In Proceedings of 10th Workshop on Rapid System Prototyping, 1999.

Hierarchische Synthese Für Die Emulation von Integrierten Steuerungssystemen

by O. Bringmann and W. Rosenstiel
In Informatik ’99 - 29. Jahrestagung Der Gesellschaft Für Informatik, Informatik Aktuell. Springer Verlag, 1999.

A VHDL Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis

by C. Hansen, O. Bringmann, and W. Rosenstiel
In Forum on Design Languages (FDL), 1999.

1998

Synchronization Detection in Multi-Process Hierarchical Synthesis

by O. Bringmann, W. Rosenstiel, and S. Reichardt
In 11th International Symposium on System Synthesis (ISSS), 1998.

Cross-Level Hierarchical High-Level Synthesis

by O. Bringmann and W. Rosenstiel
In Proceedings of Design, Automation and Test in Europe (DATE), 1998.

1997

Resource Sharing in Hierarchical Synthesis

by O. Bringmann and W. Rosenstiel
In ICCAD, 1997.

1996

Design of an Interrupt Controller with AC-8 Tools at Different Levels of Abstraction

by O. Bringmann, J. Engelhart, S. Kumar, B. Mößner, and W. Rosenstiel
In International Workshop on Logic and Architecture Synthesis, 1996.

1995

Device Selection for System Partitioning

by U. Weinmann, O. Bringmann, and W. Rosenstiel
In Eurodac, 1995.

Further Documents

Verfahren und System zur Verschlüsselung von Tastendrücken DE 10 2015 210 573 A1

by Sebastian Burg, Oliver Bringmann, and Dustin Peterson
In Deutsches Patent- und Markenamt, 2016.

Verfahren und Fahrzeugvorrichtung zur Datenfernabfrage DE 102012008283 A1

by Dustin Peterson
In Deutsches Patent- und Markenamt, 2012.