AI Hardware Design for Edge Devices

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Statistical Performance Estimation and Extrapolation

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Contribution to the Development of a Smart Video Capsule Endoscopy (VCE) System for Enhanced Gastrointestinal Diagnosis

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Abstract

Video Capsule Endoscopy (VCE) is a diagnostic tool for a minimal-invasive examination of the gastrointestinal tract. As part of an ongoing research project, we are developing a Smart VCE prototype that integrates AI-assisted image analysis, real-time sensor data processing, on-device decision making, and monitoring. To test and verify the prototype, we are simultaniously building a hardware-in-the-loop (HIL) setup.

Potential Topics

• Implementation of new hardware modules in SystemVerilog
• Extend the HIL setup
• Development and comparision of decision making approaches
• …

Requirements

• SystemVerilog
  • Successfully attended “ESES” or “MAES” (optional)
• C/C++
• Python
• Development of device driver
  • Successfully attended “PULPA” (optional)

Mapping Transformer Models on Systolic Array Architectures

Master’s Thesis / Student Research Project

Analyzing the robustness of resource-efficient DNNs

Master’s thesis

Evaluation von GPU-Sharing für virtualisierte Eingebettete Systeme

Bachelor’s Thesis / Master’s Thesis / Student Research Project