Embedded Systems

Neural Architecture Search and Performance Modeling for Infineon MCU

Master’s Thesis, Student Job, Research Project

Abstract

Neural Architecture Search (NAS) seeks to automate the design of neural networks by defining a search space of possible network variants and applying optimization algorithms to discover high-performing architectures. Hardware-aware NAS extends this goal by incorporating hardware considerations such as latency, memory usage, and supported operations into the optimization objective.

This thesis focuses on integrating an Infineon hardware MCU into the hannah NAS framework through benchmarking and measurement infrastructure. By working closely with Infineon as a manufacturing partner, you will translate expert hardware knowledge into automatic constraint generation for the search space, restricting architectures to those feasible on the target hardware. This approach extends our group’s work on constraint-solving methods for hardware-aware NAS.

The thesis contains several tasks:

  1. Set up the Infineon MCU and establish measurement infrastructure within the hannah framework
  2. Integrate device measurements into the hannah NAS pipeline for real hardware feedback
  3. Translate expert hardware knowledge from Infineon into search space constraints
  4. Optional: Develop statistical performance models for fast execution time prediction without direct hardware measurement

References

Requirements

  • Basics: Python, Git, Linux
  • Machine Learning fundamentals
  • PyTorch (recommended)
  • Successfully attended the lecture “Efficient Machine Learning in Hardware” (recommended)
  • Successfully attended the lecture “Modellierung und Analyse Eingebetteter Systeme” (recommended)

Contact

Reiber, Moritz

Jung, Alexander

Bringmann, Oliver