SMoSi: A framework for the derivation of sleep mode traces from RTL simulations
In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (): 330-335, 2016.
Keywords: integrated circuit design, integrated circuit modelling, low-power electronics, SMoSi, sleep mode trace generation, RTL simulations, idle time identification, power optimization, Ports (Computers), Redundancy, Transfer functions, Boolean functions, Data structures, Registers, Databases
Abstract
We propose a methodology for the generation of sleep modes traces. Sleep mode traces identify idle times of components in a design and are used in state-of-the-art power optimization approaches. While designers are currently forced to generate them manually, our graph-based method enables a full automation of this process. We implemented our methodology in a framework, that we call SMoSi. Experiments show that SMoSi generates sleep mode traces in reasonable time for a given design.