Ab­stract

Ab­stract—Power gat­ing (PG) is an ef­fec­tive method to re­duce leak­age cur­rents in an SoC de­sign dur­ing run-time. It dy­nam­i­cally shuts down com­po­nents using a net­work of sleep tran­sis­tors, but re­quires a de­tailed analy­sis to scale this net­work ap­pro­pri­ately with re­spect to area, wake-up time, in-rush cur­rents, volt­age drops and tran­si­tion en­er­gies. In this paper, we pre­sent a method to ef­fi­ciently de­ter­mine these key pa­ra­me­ters for any SoC de­sign and sleep tran­sis­tor net­work at gate-level to en­able the rapid ex­plo­ration of power de­sign al­ter­na­tives while pro­vid­ing suf­fi­cient ac­cu­racy for high-level de­sign ex­plo­ration. Com­pared to SPICE our ap­proach achieves a speed-up of up to 11457x for two ISCAS cir­cuits, a 32-bit mul­ti­plier and a RISC-V core, each build for a 90nm PDK. The av­er­age error com­pared to SPICE is 2.6% for peak cur­rent and 10% for wake-up en­ergy and delay.