Konstantin Lübeck

Photo of Lübeck, Konstantin

Konstantin Lübeck
University of Tübingen
Dpt. of Computer Science
Embedded Systems
Sand 13
72076 Tübingen
Germany

Telephone: +49 - (0) 70 71 - 29 - 78998
Telefax: +49 - (0) 70 71 - 29 - 50 62
E-Mail: Mail
Office: Sand 13, B225
Office hours: Open Door Policy

Konstantin Lübeck is a graduate research assistant at the Chair for Embedded Systems of the University of Tübingen. He received B.Sc. and M.Sc. degrees in Computer Science from the University of Tübingen in 2015 and 2018 respectively with a major focus on computer engineering and embedded systems. In 2016, he studied at the Uppsala University as an Erasmus exchange student. In 2017, he received a scholarship for master’s thesis from the Stiftung Industrieforschung. Since 2018, he is a lecturer of computer architecture for the Bosch Learning Company initiative at the technology transfer center Tübingen. In addition to his academic work, he is a trained mechatronics technician (certified by the German chamber of industry and commerce, IHK) and worked as a self-employed software developer.

Research Interests

Modeling, evaluation, and prediction of machine learning accelerator performance (end-to-end latency, throughput, roofline) using analytical models based on computer architecture descriptions (from register-transfer level to abstract block diagrams) and deep neural network parameters (layer types and their hyperparameters) for fast design space explorations used in neural network-hardware co-design algorithms.

Publications

2024

It’s all about PR – Smart Benchmarking AI Accelerators using Performance Representatives

by Alexander Louis-Ferdinand Jung, Jannik Steinmetz, Jonathan Gietz, Konstantin Lübeck, and Oliver Bringmann
Peer-reviewed publication, 2024.

Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators

by Mika Markus Müller, Alexander Richard Manfred Borst, Konstantin Lübeck, Alexander Louis-Ferdinand Jung, and Oliver Bringmann
Peer-reviewed publication, 2024.

2022

Work-in-Progress: Ultra-fast yet Accurate Performance Prediction for Deep Neural Network Accelerators

by Konstantin Lübeck, Alexander Louis-Ferdinand Jung, Felix Wedlich, and Oliver Bringmann
In 2022 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), pages 27-28, 2022.

Keywords: Machine Learning, Neural Networks, Performance Prediction, Neurnal Network Accelerators

Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices

by Christoph Gerum, Adrian Frischknecht, Paul Palomero Bernardo, Tobias Hald, Konstantin Lübeck, and Oliver Bringmann
In 2022 25th Euromicro Conference on Digital System Design (DSD), pages 1-8, 2022.

Keywords: Machine Learning, Neural Networks, AutoML, Neural Architecture Search

2021

APPEL - AGILA ProPErty and Dependency Description Language

by Christoph Grimm, Frank Wawrzik, Alexander Jung, Konstantin Luebeck, Sebastian Post, Johannes Koch, and Oliver Bringmann
In Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2021, 2021.

2020

UltraTrail: A Configurable Ultra-Low Power TC-ResNet AI Accelerator for Efficient Keyword Spotting

by Paul Palomero Bernardo, Christoph Gerum, Adrian Frischknecht, Konstantin Lübeck, and Oliver Bringmann
In 2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pages 1-12, 2020.

2019

A Heterogeneous and Reconfigurable Embedded Architecture for Energy-Efficient Execution of Convolutional Neural Networks

by Konstantin Lübeck and Oliver Bringmann
In Architecture of Computing Systems (ARCS 2019), 2019.

2016

Neues Konzept zur Steigerung der Zuverlaessigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs

by Konstantin Luebeck, David Morgenstern, Thomas Schweizer, Dustin Peterson, Wolfgang Rosenstiel, and Oliver Bringmann
In Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016, 2016.

Research projects

GENIAL!

Scale4Edge

Teaching

Advanced Topics in Embedded Systems	Summer 2019
Efficient Machine Learning in Hardware	Summer 2021 Summer 2022
Entwurf und Synthese Eingebetteter Systeme	Summer 2019
Moderne Architekturen Eingebetteter Systeme	Winter 2018 Winter 2019 Winter 2020
Parallele Rechnerarchitekturen	Summer 2020 Summer 2021 Winter 2022 Winter 2023
Proseminar: Moderne Architekturen Eingebetteter Systeme	Winter 2021
Teamprojekt: Implementierung einer RISC-V Rechnerarchitektur	Winter 2024
Teamprojekt: Interaktiver Rechnerarchitektursimulator	Summer 2023

Thesis Topics

Open Thesis Topics

Evaluation of AutoML Methods for Performance Estimation

Bachelor’s Thesis / Student Research Project

Performance Modeling of the NVIDIA Deep-Learning Accelerator (NVDLA) using Performance Representatives

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Automatic Translation of Python Instruction Behaviors into C++

Bachelor’s Thesis / Student Research Project

Modeling the Nvidia NVDLA Machine Learning Accelerator in ACADL for Performance Predictions

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Modeling DRAM in ACADL for Performance Predictions

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Assigned Thesis Topics

Cross-Architecture Performance Prediction

Bachelor’s Thesis / Master’s Thesis / Student Research Project

ACADL to Verilog Translation

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Finished Thesis Topics

Transferring Fine-grained DNN Accelerator Architecture Performance Models to Coarse-grained Models

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Modeling the VTA Machine Learning Accelerator in ACADL for Performance Predictions

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Implementation of an Abstract Machine Learning Accelerator Generator based on ACADL

Bachelor’s Thesis / Student Research Project

Implementation and Training of a Machine Learning Model to Predict Cache Hit/Miss Rates

Bachelor’s Thesis / Student Research Project

Implementation of the Pico-CNN Deep Learning Inference Framework for RISC-V

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Deployment of a Deep Learning Face-Recognition System on a Raspberry Pi using Pico-CNN

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Design and Implementation of a WYSIWYG Web App for Abstract HW/SW Description Languages

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Design and Implementation of an Arduino Based GPIO Multiplexer

Bachelor’s Thesis

Design and Implementation of an Instruction Trace Translator

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Entwicklung eines Hardwarebeschleunigers für Voice-Activity-Detection

Bachelorthesis

Refactoring und Synthese des superskalaren TÜRI5X-Prozessorkerns

Bachelorthesis

Implementation eines analytischen Performance-Modells für den Prozessorkern des Broadcom BCM2836

Bachelor’s Thesis

Implementation of the Pico-CNN Deep Learning Inference Framework in OpenCL for Embedded Devices

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Erstellung eines Datensatzes mit Keywords und Hintergrundgeräuschen

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Erweiterung des PULP-SDKs um die Unterstützung des LLVM Compilers

Bachelor’s Thesis

Entwurf und Implementierung einer Cache-Architektur für den PULPissimo SoC

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Implementation und Evaluierung der Minerva-Beschleunigerarchitektur für DNNs

Bachelor’s Thesis

Integration eines On-Chip CAN-Controllers in den PULPissimo SoC

Bachelor’s Thesis

Entwurf und Implementation eines Hardware-Beschleunigers für TC-ResNet8

Master’s Thesis

Erweiterung des RI5CY-Prozessorkerns um dynamische Verfahren zur Sprungvorhersage

Bachelor’s Thesis

Entwurf und Implementation einer energie- und flächensparenden ALU für den RI5CY-Prozessorkern

Bachelor’s Thesis

Erweiterung des RI5CY-Cores um eine Issue Pipeline-Stufe zur superskalaren Ausführung von Instruktionen

Bachelor’s Thesis

News

Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices

The paper “Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices” has been accepted at the 25th Euromicro Conference on Digital System Design (DSD), pages 1-8, 2022. Keywords: Machine Learning, Neural Networks, AutoML, Neural Architecture Search

Scale4Edge - Skalierbare Infrastruktur für Edge-Computing

Neues BMBF-Projekt in der Informatik der Universität Tübingen zur Entwicklung und Bereitstellung eines Ökosystems für eine skalierbare und flexibel erweiterbare Edge-Computing-Plattform basierend auf der freien RISC-V-Instruktionssatzarchitektur.

GENIAL! - Gemeinsame Elektronik-Roadmap für Innovationen der automobilen Wertschöpfungskette

Neues BMBF-Projekt in der Informatik der Universität Tübingen zur Erstellung einer automotive Innovations-Roadmap. BMBF und Industrie fördern Vorhaben mit insgesamt 19,6 Millionen Euro.