Compiler-aware AI Hardware Design for Edge Devices

by Paul Palomero Bernardo, Patrick Schmid, Christoph Gerum, and Oliver Bringmann
In Proceedings of the 8th International Workshop on Edge Systems, Analytics and Networking, pages 31–36. Association for Computing Machinery, 2025.

Keywords: edge computing, hardware accelerator, deep learning compiler

Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators

by Konstantin Lübeck, Alexander Louis-Ferdinand Jung, Felix Wedlich, Mika Markus Müller, Federico Nicolás Peccia, Felix Thömmes, Jannik Steinmetz, Valentin Biermaier, Adrian Frischknecht, Paul Palomero Bernardo, and Oliver Bringmann
In ACM Trans. Embed. Comput. Syst. 24(2). Association for Computing Machinery, 2025.

Keywords: Deep neural networks, performance estimation, analytical model

GOURD: Tensorizing Streaming Applications to Generate Multi-Instance Compute Platforms

by Patrick Schmid, Paul Palomero Bernardo, Christoph Gerum, and Oliver Bringmann
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43(11): 4166-4177, 2024.

Keywords: Integrated circuits, Actuators, Design automation, Shape, Memory architecture, Focusing, Edge AI, Hardware, Sensors, Data orchestration, hardware platform generation, multidimensional data flow, synchronization

Energy-Efficient Seizure Detection Suitable for Low-Power Applications

by Julia Werner, Bhavya Kohli, Paul Palomero Bernardo, Christoph Gerum, and Oliver Bringmann
In IEEE International Joint Conference on Neural Networks (IJCNN), 2024.

A scalable risc-v hardware platform for intelligent sensor processing

by Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, and others
In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–5, 2024.

A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator

by Oliver Bause, Paul Palomero Bernardo, and Oliver Bringmann
In MBMV 2024; 27. Workshop, pages 31–40, 2024.

The Scale4Edge RISC-V Ecosystem

by Wolfgang Ecker, Peer Adelt, Wolfgang Mueller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, and Wolfgang Kunz
In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 808-813, 2022.

Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices

by Christoph Gerum, Adrian Frischknecht, Paul Palomero Bernardo, Tobias Hald, Konstantin Lübeck, and Oliver Bringmann
In 2022 25th Euromicro Conference on Digital System Design (DSD), pages 1-8, 2022.

Keywords: Machine Learning, Neural Networks, AutoML, Neural Architecture Search

Automated HW/SW Co-Design for Edge AI: State, Challenges and Steps Ahead

by Oliver Bringmann, Wolfgang Ecker, Ingo Feldner, Adrian Frischknecht, Christoph Gerum, Timo Hämäläinen, Muhammad Abdullah Hanif, Michael J. Klaiber, Daniel Mueller-Gritschneder, Paul Palomero Bernardo, Sebastian Prebeck, and Muhammad Shafique
In Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis, pages 11–20. Association for Computing Machinery, 2021.

UltraTrail: A Configurable Ultra-Low Power TC-ResNet AI Accelerator for Efficient Keyword Spotting

by Paul Palomero Bernardo, Christoph Gerum, Adrian Frischknecht, Konstantin Lübeck, and Oliver Bringmann
In 2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pages 1-12, 2020.

AI Hardware Design for Edge Devices

Bachelor’s Thesis / Master’s Thesis / Student Research Project

Rework of the NanEyeC camera controller and integration of the controller into an image processing pipeline

Master’s Thesis

Extending the Pulpissimo Architecture for Enhanced Capsule Endoscopy: SPI Interface and AI Capabilities

Master’s Thesis

Template-Based DSP Accelerator for Efficient Audio Processing in ML applications

Master’s Thesis

Exploration und Analyse von KI-Beschleunigern mit dem Entwurfsraumexplorationswerkzeug ZigZag

Bachelor’s Thesis

Entwurf und Synthese eines Hardware-Controllers für das NanEyeC Kamera-Modul

Bachelor’s Thesis

Hardware Acceleration of Convolutional Neural Networks: A Template-based Design Exploration

Master’s Thesis

Design of a Memory Framework for Neural Network Accelerators that Utilizes Their Calculable Memory Access Patterns

Master’s Thesis

Entwicklung eines Prototypen für die Sirenenpräsenzerkennung mit dem UltraTrail-Beschleuniger

Bachelorthesis

Design of Runtime Adjustable Fixed-point Units for UltraTrail

Research Project

Design and implementation of a bit-serial accelerator architecture based on UltraTrail

Internship

Erweiterung von UltraTrail um digitale Signalverarbeitung für die Berechnung von MFCC-Features

Masterthesis

Extension of UltraTrail - a scalable and low power CNN accelerator

Master’s Thesis

Erweiterung von UltraTrail um Grouped-, Separated- und Sinc-Convolutions

Masterthesis