As­signed to Simon Müller.

Mas­ter’s the­sis

Soft­ware con­trolled power man­age­ment is a stan­dard tech­nique to lower the en­ergy con­sump­tion of com­put­ers of all sizes. Due to the huge range of dif­fer­ent ap­pli­ca­tions ex­e­cuted on end-user sys­tems, the power man­age­ment is often gov­erned by the op­er­at­ing sys­tem. For em­bed­ded sys­tems how­ever, the ap­pli­ca­tion code is often known and well-de­fined at the sys­tem de­sign stage. As a re­sult, the po­ten­tial for more pre­cise and spe­cific power-sav­ing op­ti­miza­tions arises. Po­si­tions in the soft­ware code for power mode tran­si­tions can be iden­ti­fied using sta­tic analy­sis or sim­u­la­tion re­sults of the soft­ware.

Within this pro­ject an ex­ten­sion of a Power Man­age­ment Con­troller (PMC) will be im­ple­mented in Ver­ilog. This PMC will be soft­ware-con­fig­urable and trig­gers power mode changes in ac­cor­dance with a pre-con­fig­ured sched­ule.

Con­tact

Kuhn, Michael

Schmid, Patrick

Bring­mann, Oliver