Extension of UltraTrail - a scalable and low power CNN accelerator
Master’s Thesis
Abstract
Our state-of-the-art 1d CNN accelerator UltraTrail (https://ieeexplore.ieee.org/document/9216480) has been designed for (audio) keyword spotting using the TC-Resnet8 (https://arxiv.org/pdf/1904.03814.pdf). We have many ideas to improve its energy efficiency. This ranges from minor RTL changes like memory splitting to improve the clock and power gating ability to completely new functions like separable convolutions and dilation. Depending on your interests, you can self characterize standard cells in 22FDX technology and perform a design space exploration to improve energy efficiency without changing one line of RTL code. The accelerator is written in SystemVerilog.
Requirements
- Sucessfully passed ESES lecture or knowledge of hardware design using Verilog or VHDL.
- Knowledge of neural networks is beneficial but not necessary.