Embedded Systems

Evaluation of Different Communication Architectures for the PULPissimo SoC

Master’s Thesis


In this thesis the communication of the RI5CY processor core with the peripheral devices (memory, hardware accelerator, I/O) shall be investigated and an alternative communication architecture with focus on energy efficiency shall be implemented.


  • Sucessfully passed ESES lecture or knowledge of hardware design using Verilog or VHDL


Bringmann, Oliver

Frischknecht, Adrian

Lübeck, Konstantin